Countries

Lower Canada

Lower Canada

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Province of Lower Canada
Province du Bas-Canada  (French)
1791–1841
Flag of Lower Canada
Civil ensign (1801 onward)
Évolution territoriale du Bas-Canada.gif
Status British colony
Capital Quebec City
Common languages FrenchEnglish
Government Château Clique oligarchy
under a
Constitutional monarchy
Sovereign
• 1791–1820
George III
• 1820–1830
George IV
• 1830–1837
William IV
• 1837–1841
Victoria
Lieutenant-Governor and Executive Council of Lower Canada
Legislature Parliament of Lower Canada
Legislative Council
Legislative Assembly
Historical era British Era
26 December 1791
10 February 1841
Area
1839[1] 534,185 km2 (206,250 sq mi)
Population
• 1839[1]
c. 700,000
Currency Canadian pound

Preceded by

Succeeded by
Province of Quebec (1763–1791)
Province of Canada
Colony of Newfoundland
Today part of

The Province of Lower Canada (Frenchprovince du Bas-Canada) was a British colony on the lower Saint Lawrence River and the shores of the Gulf of Saint Lawrence (1791–1841). It covered the southern portion of the current Province of Quebec and the Labrador region of the current Province of Newfoundland and Labrador (until the Labrador region was transferred to Newfoundland in 1809).[2]

Lower Canada consisted of part of the former colony of Canada of New France, conquered by Great Britain in the Seven Years’ War ending in 1763 (also called the French and Indian War in the United States). Other parts of New France conquered by Britain became the Colonies of Nova ScotiaNew Brunswick, and Prince Edward Island.

The Province of Lower Canada was created by the Constitutional Act 1791 from the partition of the British colony of the Province of Quebec (1763–1791)[3] into the Province of Lower Canada and the Province of Upper Canada. The prefix “lower” in its name refers to its geographic position farther downriver from the headwaters of the St. Lawrence River than its contemporary Upper Canada, present-day southern Ontario.

Lower Canada was abolished in 1841 when it and adjacent Upper Canada were united into the Province of Canada.[4]

Rebellion[edit]

Like Upper Canada, there was significant political unrest. Twenty-two years after the invasion by the Americans in the War of 1812, a rebellion now challenged the British rule of the predominantly French population. After the Patriote Rebellion in the Rebellions of 1837–1838[5] were crushed by the British Army and Loyal volunteers, the 1791 Constitution was suspended on 27 March 1838 and a special council was appointed to administer the colony. An abortive attempt by revolutionary Robert Nelson to declare a Republic of Lower Canada was quickly thwarted.

The provinces of Lower Canada and Upper Canada were combined as the United Province of Canada in 1841, when the Act of Union 1840 came into force. Their separate legislatures were combined into a single parliament with equal representation for both constituent parts, even though Lower Canada had a greater population.[6]

Constitution[edit]

Constitution of Lower Canada in 1791

The Province of Lower Canada inherited the mixed set of French and English institutions that existed in the Province of Quebec during the 1763–1791 period and which continued to exist later in Canada-East (1841–1867) and ultimately in the current Province of Quebec (since 1867).

Population[edit]

Lower Canada was populated mainly by Canadiens, an ethnic group who trace their ancestry to French colonists who settled in Canada from the 17th century onward.

Population of Lower Canada, 1806 to 1841
Year Census estimate[9]
1806 250,000
1814 335,000
1822 427,465
1825 479,288
1827 473,475
1831 553,134
1841 650,000

Transportation[edit]

Current route marker seen along the Chemin

Travelling around Lower Canada was mainly by water along the St. Lawrence River. On land the only long-distance route was the Chemin du Roy or King’s Highway, built in the 1730s by New France.[10] The King’s Highway was, in addition to the mail route, the primary means of long-distance passenger travel until steamboats (1815) and railways (1850s) began to challenge the royal road.[10] The royal road’s importance waned after the 1850s and would not re-emerge as a key means of transportation until the modern highway system of Quebec was created in the 20th century.

See also[edit]

R

Uncategorized

Flow control (data)

Flow control (data)

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In data communicationsflow control is the process of managing the rate of data transmission between two nodes to prevent a fast sender from overwhelming a slow receiver. It provides a mechanism for the receiver to control the transmission speed, so that the receiving node is not overwhelmed with data from transmitting node. Flow control should be distinguished from congestion control, which is used for controlling the flow of data when congestion has actually occurred.[1] Flow control mechanisms can be classified by whether or not the receiving node sends feedback to the sending node.

Flow control is important because it is possible for a sending computer to transmit information at a faster rate than the destination computer can receive and process it. This can happen if the receiving computers have a heavy traffic load in comparison to the sending computer, or if the receiving computer has less processing power than the sending computer.

Stop-and-wait[edit]

Stop-and-wait flow control is the simplest form of flow control. In this method the message is broken into multiple frames, and the receiver indicates its readiness to receive a frame of data. The sender waits for a receipt acknowledgement (ACK) after every frame for a specified time (called a time out). The receiver sends the ACK to let the sender know that the frame of data was received correctly. The sender will then send the next frame only after the ACK.

Operations[edit]

  1. Sender: Transmits a single frame at a time.
  2. Sender waits to receive ACK within time out.
  3. Receiver: Transmits acknowledgement (ACK) as it receives a frame.
  4. Go to step 1 when ACK is received, or time out is hit.

If a frame or ACK is lost during transmission then the frame is re-transmitted. This re-transmission process is known as ARQ (automatic repeat request).

The problem with Stop-and-wait is that only one frame can be transmitted at a time, and that often leads to inefficient transmission, because until the sender receives the ACK it cannot transmit any new packet. During this time both the sender and the channel are unutilised.

Pros and cons of stop and wait[edit]

Pros

The only advantage of this method of flow control is its simplicity.

Cons

The sender needs to wait for the ACK after every frame it transmits. This is a source of inefficiency, and is particularly bad when the propagation delay is much longer than the transmission delay.[2]

Stop and wait can also create inefficiencies when sending longer transmissions.[3] When longer transmissions are sent there is more likely chance for error in this protocol. If the messages are short the errors are more likely to be detected early. More inefficiency is created when single messages are broken into separate frames because it makes the transmission longer.[4]

Sliding Window[edit]

A method of flow control in which a receiver gives a transmitter permission to transmit data until a window is full. When the window is full, the transmitter must stop transmitting until the receiver advertises a larger window.[5]

Sliding-window flow control is best utilized when the buffer size is limited and pre-established. During a typical communication between a sender and a receiver the receiver allocates buffer space for n frames (n is the buffer size in frames). The sender can send and the receiver can accept n frames without having to wait for an acknowledgement. A sequence number is assigned to frames in order to help keep track of those frames which did receive an acknowledgement. The receiver acknowledges a frame by sending an acknowledgement that includes the sequence number of the next frame expected. This acknowledgement announces that the receiver is ready to receive n frames, beginning with the number specified. Both the sender and receiver maintain what is called a window. The size of the window is less than or equal to the buffer size.

Sliding window flow control has a far better performance than stop-and-wait flow control. For example, in a wireless environment if data rates are low and noise level is very high, waiting for an acknowledgement for every packet that is transferred is not very feasible. Therefore, transferring data as a bulk would yield a better performance in terms of higher throughput.

Sliding window flow control is a point to point protocol assuming that no other entity tries to communicate until the current data transfer is complete. The window maintained by the sender indicates which frames he can send. The sender sends all the frames in the window and waits for an acknowledgement (as opposed to acknowledging after every frame). The sender then shifts the window to the corresponding sequence number, thus indicating that frames within the window starting from the current sequence number can be sent.

Go Back N[edit]

An automatic repeat request (ARQ) algorithm, used for error correction, in which a negative acknowledgement (NAK) causes retransmission of the word in error as well as the next N–1 words. The value of N is usually chosen such that the time taken to transmit the N words is less than the round trip delay from transmitter to receiver and back again. Therefore, a buffer is not needed at the receiver.

The normalized propagation delay (a) = ​propagation time (Tp)transmission time (Tt), where Tp = Length (L) over propagation velocity (V) and Tt = bitrate (r) over Framerate (F). So that a =​LFVr.

To get the utilization you must define a window size (N). If N is greater than or equal to 2a + 1 then the utilization is 1 (full utilization) for the transmission channel. If it is less than 2a + 1 then the equation ​N1+2a must be used to compute utilization.[6]

Selective Repeat[edit]

Selective Repeat is a connection oriented protocol in which both transmitter and receiver have a window of sequence numbers. The protocol has a maximum number of messages that can be sent without acknowledgement. If this window becomes full, the protocol is blocked until an acknowledgement is received for the earliest outstanding message. At this point the transmitter is clear to send more messages.[7]

Comparison[edit]

This section is geared towards the idea of comparing Stop-and-waitSliding Window with the subsets of Go Back N and Selective Repeat.

Stop-and-Wait[edit]

Error free: {\displaystyle {\frac {1}{2a+1}}}.[citation needed]

With errors: {\displaystyle {\frac {1-P}{2a+1}}}.[citation needed]

Selective Repeat[edit]

We define throughput T as the average number of blocks communicated per transmitted block. It is more convenient to calculate the average number of transmissions necessary to communicate a block, a quantity we denote by 0, and then to determine T from the equation {\displaystyle T={\frac {1}{b}}}.[citation needed]

Transmit flow control[edit]

Transmit flow control may occur:

The transmission rate may be controlled because of network or DTE requirements. Transmit flow control can occur independently in the two directions of data transfer, thus permitting the transfer rates in one direction to be different from the transfer rates in the other direction. Transmit flow control can be

Flow control can be performed

Hardware flow control[edit]

In common RS-232 there are pairs of control lines which are usually referred to as hardware flow control:

Hardware flow control is typically handled by the DTE or “master end”, as it is first raising or asserting its line to command the other side:

  • In the case of RTS control flow, DTE sets its RTS, which signals the opposite end (the slave end such as a DCE) to begin monitoring its data input line. When ready for data, the slave end will raise its complementary line, CTS in this example, which signals the master to start sending data, and for the master to begin monitoring the slave’s data output line. If either end needs to stop the data, it lowers its respective “data readiness” line.
  • For PC-to-modem and similar links, in the case of DTR flow control, DTR/DSR are raised for the entire modem session (say a dialup internet call where DTR is raised to signal the modem to dial, and DSR is raised by the modem when the connection is complete), and RTS/CTS are raised for each block of data.

An example of hardware flow control is a Half-duplex radio modem to computer interface. In this case, the controlling software in the modem and computer may be written to give priority to incoming radio signals such that outgoing data from the computer is paused by lowering CTS if the modem detects a reception.

  • Polarity:
    • RS-232 level signals are inverted by the driver ICs, so line polarity is TxD-, RxD-, CTS+, RTS+ (Clear to send when HI, Data 1 is a LO)
    • for microprocessor pins the signals are TxD+, RxD+, CTS-, RTS- (Clear to send when LO, Data 1 is a HI)

Software flow control[edit]

Conversely, XON/XOFF is usually referred to as software flow control.

Open-loop flow control[edit]

The open-loop flow control mechanism is characterized by having no feedback between the receiver and the transmitter. This simple means of control is widely used. The allocation of resources must be a “prior reservation” or “hop-to-hop” type.

Open-loop flow control has inherent problems with maximizing the utilization of network resources. Resource allocation is made at connection setup using a CAC (Connection Admission Control) and this allocation is made using information that is already “old news” during the lifetime of the connection. Often there is an over-allocation of resources and reserved but unused capacities are wasted. Open-loop flow control is used by ATM in its CBRVBR and UBR services (see traffic contract and congestion control).[1]

Open-loop flow control incorporates two controls; the controller and a regulator. The regulator is able to alter the input variable in response to the signal from the controller. An open-loop system has no feedback or feed forward mechanism, so the input and output signals are not directly related and there is increased traffic variability. There is also a lower arrival rate in such system and a higher loss rate. In an open control system, the controllers can operate the regulators at regular intervals, but there is no assurance that the output variable can be maintained at the desired level. While it may be cheaper to use this model, the open-loop model can be unstable.

Closed-loop flow control[edit]

The closed-loop flow control mechanism is characterized by the ability of the network to report pending network congestion back to the transmitter. This information is then used by the transmitter in various ways to adapt its activity to existing network conditions. Closed-loop flow control is used by ABR (see traffic contract and congestion control).[1] Transmit flow control described above is a form of closed-loop flow control.

This system incorporates all the basic control elements, such as, the sensor, transmitter, controller and the regulator. The sensor is used to capture a process variable. The process variable is sent to a transmitter which translates the variable to the controller. The controller examines the information with respect to a desired value and initiates a correction action if required. The controller then communicates to the regulator what action is needed to ensure that the output variable value is matching the desired value. Therefore, there is a high degree of assurance that the output variable can be maintained at the desired level. The closed-loop control system can be a feedback or a feed forward system:

A feedback closed-loop system has a feed-back mechanism that directly relates the input and output signals. The feed-back mechanism monitors the output variable and determines if additional correction is required. The output variable value that is fed backward is used to initiate that corrective action on a regulator. Most control loops in the industry are of the feedback type.

In a feed-forward closed loop system, the measured process variable is an input variable. The measured signal is then used in the same fashion as in a feedback system.

The closed-loop model produces lower loss rate and queuing delays, as well as it results in congestion-responsive traffic. The closed-loop model is always stable, as the number of active lows is bounded.

See also[edit]

References

Uncategorized

OSI model

OSI model

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The Open Systems Interconnection model (OSI model) is a conceptual model that characterises and standardises the communication functions of a telecommunication or computing system without regard to its underlying internal structure and technology. Its goal is the interoperability of diverse communication systems with standard communication protocols. The model partitions a communication system into abstraction layers.

A layer serves the layer above it and is served by the layer below it. For example, a layer that provides error-free communications across a network provides the path needed by applications above it, while it calls the next lower layer to send and receive packets that constitute the contents of that path.

The model is a product of the Open Systems Interconnection project at the International Organization for Standardization (ISO).

Communication in the OSI-Model (example with layers 3 to 5)

History[edit]

In the early- and mid-1970s, networking was largely either government-sponsored (NPL network in the UK, ARPANET in the US, CYCLADES in France) or vendor-developed with proprietary standards, such as IBM‘s Systems Network Architecture and Digital Equipment Corporation‘s DECnetPublic data networks were only just beginning to emerge, and these began to use the X.25 standard in the late 1970s.[1][2]

The Experimental Packet Switched System in the UK circa 1973-5 identified the need for defining higher level protocols.[1] The UK National Computing Centre publication ‘Why Distributed Computing’ which came from considerable research into future configurations for computer systems,[3] resulted in the UK presenting the case for an international standards committee to cover this area at the ISO meeting in Sydney in March 1977.[4]

Beginning in 1977, the International Organization for Standardization (ISO) conducted a program to develop general standards and methods of networking. A similar process evolved at the International Telegraph and Telephone Consultative Committee (CCITT, from French: Comité Consultatif International Téléphonique et Télégraphique). Both bodies developed documents that defined similar networking models. The OSI model was first defined in raw form in Washington, DC in February 1978 by Hubert Zimmermann of France and the refined but still draft standard was published by the ISO in 1980.[5]

The drafters of the reference model had to contend with many competing priorities and interests. The rate of technological change made it necessary to define standards that new systems could converge to rather than standardizing procedures after the fact; the reverse of the traditional approach to developing standards.[6] Although not a standard itself, it was a framework in which future standards could be defined.[7]

In 1983, the CCITT and ISO documents were merged to form The Basic Reference Model for Open Systems Interconnection, usually referred to as the Open Systems Interconnection Reference ModelOSI Reference Model, or simply OSI model. It was published in 1984 by both the ISO, as standard ISO 7498, and the renamed CCITT (now called the Telecommunications Standardization Sector of the International Telecommunication Union or ITU-T) as standard X.200.

OSI had two major components, an abstract model of networking, called the Basic Reference Model or seven-layer model, and a set of specific protocols. The OSI reference model was a major advance in the teaching of network concepts. It promoted the idea of a consistent model of protocol layers, defining interoperability between network devices and software.

The concept of a seven-layer model was provided by the work of Charles Bachman at Honeywell Information Systems.[8] Various aspects of OSI design evolved from experiences with the NPL network, ARPANET, CYCLADES, EIN, and the International Networking Working Group (IFIP WG6.1). In this model, a networking system was divided into layers. Within each layer, one or more entities implement its functionality. Each entity interacted directly only with the layer immediately beneath it and provided facilities for use by the layer above it.

The OSI standards documents are available from the ITU-T as the X.200-series of recommendations.[9] Some of the protocol specifications were also available as part of the ITU-T X series. The equivalent ISO and ISO/IEC standards for the OSI model were available from ISO. Not all are free of charge.[10]

OSI was an industry effort, attempting to get industry participants to agree on common network standards to provide multi-vendor interoperability.[11] It was common for large networks to support multiple network protocol suites, with many devices unable to interoperate with other devices because of a lack of common protocols. For a period in the late 1980s and early 1990s, engineers, organizations and nations became polarized over the issue of which standard, the OSI model or the Internet protocol suite, would result in the best and most robust computer networks.[4][12][13] However, while OSI developed its networking standards in the late 1980s,[14][15] TCP/IP came into widespread use on multi-vendor networks for internetworking.

The OSI model is still used as a reference for teaching and documentation;[16] however, the OSI protocols originally conceived for the model did not gain popularity. Some engineers argue the OSI reference model is still relevant to cloud computing.[17] Others say the original OSI model doesn’t fit today’s networking protocols and have suggested instead a simplified approach.[18]

Definitions[edit]

Communication protocols enable an entity in one host to interact with a corresponding entity at the same layer in another host. Service definitions, like the OSI Model, abstractly describe the functionality provided to an (N)-layer by an (N-1) layer, where N is one of the seven layers of protocols operating in the local host.

At each level N, two entities at the communicating devices (layer N peers) exchange protocol data units (PDUs) by means of a layer N protocol. Each PDU contains a payload, called the service data unit (SDU), along with protocol-related headers or footers.

Data processing by two communicating OSI-compatible devices proceeds as follows:

  1. The data to be transmitted is composed at the topmost layer of the transmitting device (layer N) into a protocol data unit (PDU).
  2. The PDU is passed to layer N-1, where it is known as the service data unit (SDU).
  3. At layer N-1 the SDU is concatenated with a header, a footer, or both, producing a layer N-1 PDU. It is then passed to layer N-2.
  4. The process continues until reaching the lowermost level, from which the data is transmitted to the receiving device.
  5. At the receiving device the data is passed from the lowest to the highest layer as a series of SDUs while being successively stripped from each layer’s header or footer until reaching the topmost layer, where the last of the data is consumed.

Standards documents[edit]

The OSI model was defined in ISO/IEC 7498 which consists of the following parts:

  • ISO/IEC 7498-1 The Basic Model
  • ISO/IEC 7498-2 Security Architecture
  • ISO/IEC 7498-3 Naming and addressing
  • ISO/IEC 7498-4 Management framework

ISO/IEC 7498-1 is also published as ITU-T Recommendation X.200.

Layer architecture[edit]

The recommendation X.200 describes seven layers, labelled 1 to 7. Layer 1 is the lowest layer in this model.

OSI model
Layer Protocol data unit (PDU) Function[19]
Host
layers
7 Application Data High-level APIs, including resource sharing, remote file access
6 Presentation Translation of data between a networking service and an application; including character encodingdata compression and encryption/decryption
5 Session Managing communication sessions, i.e., continuous exchange of information in the form of multiple back-and-forth transmissions between two nodes
4 Transport SegmentDatagram Reliable transmission of data segments between points on a network, including segmentationacknowledgement and multiplexing
Media
layers
3 Network Packet Structuring and managing a multi-node network, including addressingrouting and traffic control
2 Data link Frame Reliable transmission of data frames between two nodes connected by a physical layer
1 Physical Symbol Transmission and reception of raw bit streams over a physical medium

Layer 1: Physical Layer[edit]

The physical layer is responsible for the transmission and reception of unstructured raw data between a device and a physical transmission medium. It converts the digital bits into electrical, radio, or optical signals. Layer specifications define characteristics such as voltage levels, the timing of voltage changes, physical data rates, maximum transmission distances, modulation scheme, channel access method and physical connectors. This includes the layout of pinsvoltages, line impedance, cable specifications, signal timing and frequency for wireless devices. Bit rate control is done at the physical layer and may define transmission mode as simplexhalf duplex, and full duplex. The components of a physical layer can be described in terms of a network topology. Physical layer specifications are included in the specifications for the ubiquitous BluetoothEthernet, and USB standards. An example of a less well-known physical layer specification would be for the CAN standard.

Layer 2: Data Link Layer[edit]

The data link layer provides node-to-node data transfer—a link between two directly connected nodes. It detects and possibly corrects errors that may occur in the physical layer. It defines the protocol to establish and terminate a connection between two physically connected devices. It also defines the protocol for flow control between them.

IEEE 802 divides the data link layer into two sublayers:[20]

  • Medium access control (MAC) layer – responsible for controlling how devices in a network gain access to a medium and permission to transmit data.
  • Logical link control (LLC) layer – responsible for identifying and encapsulating network layer protocols, and controls error checking and frame synchronization.

The MAC and LLC layers of IEEE 802 networks such as 802.3 Ethernet802.11 Wi-Fi, and 802.15.4 ZigBee operate at the data link layer.

The Point-to-Point Protocol (PPP) is a data link layer protocol that can operate over several different physical layers, such as synchronous and asynchronous serial lines.

The ITU-T G.hn standard, which provides high-speed local area networking over existing wires (power lines, phone lines and coaxial cables), includes a complete data link layer that provides both error correction and flow control by means of a selective-repeat sliding-window protocol.

Security, specifically (authenticated) encryption, at this layer can be applied with MACSec

Layer 3: Network Layer[edit]

The network layer provides the functional and procedural means of transferring variable length data sequences (called packets) from one node to another connected in “different networks”. A network is a medium to which many nodes can be connected, on which every node has an address and which permits nodes connected to it to transfer messages to other nodes connected to it by merely providing the content of a message and the address of the destination node and letting the network find the way to deliver the message to the destination node, possibly routing it through intermediate nodes. If the message is too large to be transmitted from one node to another on the data link layer between those nodes, the network may implement message delivery by splitting the message into several fragments at one node, sending the fragments independently, and reassembling the fragments at another node. It may, but does not need to, report delivery errors.

Message delivery at the network layer is not necessarily guaranteed to be reliable; a network layer protocol may provide reliable message delivery, but it need not do so.

A number of layer-management protocols, a function defined in the management annex, ISO 7498/4, belong to the network layer. These include routing protocols, multicast group management, network-layer information and error, and network-layer address assignment. It is the function of the payload that makes these belong to the network layer, not the protocol that carries them.[21]

Layer 4: Transport Layer[edit]

The transport layer provides the functional and procedural means of transferring variable-length data sequences from a source to a destination host, while maintaining the quality of service functions.

The transport layer controls the reliability of a given link through flow control, segmentation/desegmentation, and error control. Some protocols are state- and connection-oriented. This means that the transport layer can keep track of the segments and retransmit those that fail delivery. The transport layer also provides the acknowledgement of the successful data transmission and sends the next data if no errors occurred. The transport layer creates segments out of the message received from the application layer. Segmentation is the process of dividing a long message into smaller messages.

OSI defines five classes of connection-mode transport protocols ranging from class 0 (which is also known as TP0 and provides the fewest features) to class 4 (TP4, designed for less reliable networks, similar to the Internet). Class 0 contains no error recovery and was designed for use on network layers that provide error-free connections. Class 4 is closest to TCP, although TCP contains functions, such as the graceful close, which OSI assigns to the session layer. Also, all OSI TP connection-mode protocol classes provide expedited data and preservation of record boundaries. Detailed characteristics of TP0-4 classes are shown in the following table:[22]

Feature name TP0 TP1 TP2 TP3 TP4
Connection-oriented network Yes Yes Yes Yes Yes
Connectionless network No No No No Yes
Concatenation and separation No Yes Yes Yes Yes
Segmentation and reassembly Yes Yes Yes Yes Yes
Error recovery No Yes Yes Yes Yes
Reinitiate connectiona No Yes No Yes No
Multiplexing / demultiplexing over single virtual circuit No No Yes Yes Yes
Explicit flow control No No Yes Yes Yes
Retransmission on timeout No No No No Yes
Reliable transport service No Yes No Yes Yes
a If an excessive number of PDUs are unacknowledged.

An easy way to visualize the transport layer is to compare it with a post office, which deals with the dispatch and classification of mail and parcels sent. A post office inspects only the outer envelope of mail to determine its delivery. Higher layers may have the equivalent of double envelopes, such as cryptographic presentation services that can be read by the addressee only. Roughly speaking, tunnelling protocols operate at the transport layer, such as carrying non-IP protocols such as IBM‘s SNA or Novell‘s IPX over an IP network, or end-to-end encryption with IPsec. While Generic Routing Encapsulation (GRE) might seem to be a network-layer protocol, if the encapsulation of the payload takes place only at the endpoint, GRE becomes closer to a transport protocol that uses IP headers but contains complete Layer 2 frames or Layer 3 packets to deliver to the endpoint. L2TP carries PPP frames inside transport segments.

Although not developed under the OSI Reference Model and not strictly conforming to the OSI definition of the transport layer, the Transmission Control Protocol (TCP) and the User Datagram Protocol (UDP) of the Internet Protocol Suite are commonly categorized as layer-4 protocols within OSI.

Transport Layer Security (TLS) provide security at this layer.

Layer 5: Session Layer[edit]

The session layer controls the dialogues (connections) between computers. It establishes, manages and terminates the connections between the local and remote application. It provides for full-duplexhalf-duplex, or simplex operation, and establishes procedures for checkpointing, suspending, restarting, and terminating a session. In the OSI model, this layer is responsible for gracefully closing a session, which is handled in the Transmission Control Protocol at the transport layer in the Internet Protocol Suite. This layer is also responsible for session checkpointing and recovery, which is not usually used in the Internet Protocol Suite. The session layer is commonly implemented explicitly in application environments that use remote procedure calls.

Layer 6: Presentation Layer[edit]

The presentation layer establishes context between application-layer entities, in which the application-layer entities may use different syntax and semantics if the presentation service provides a mapping between them. If a mapping is available, presentation protocol data units are encapsulated into session protocol data units and passed down the protocol stack.

This layer provides independence from data representation by translating between application and network formats. The presentation layer transforms data into the form that the application accepts. This layer formats data to be sent across a network. It is sometimes called the syntax layer.[23] The presentation layer can include compression functions.[24] The Presentation Layer negotiates the Transfer Syntax.

The original presentation structure used the Basic Encoding Rules of Abstract Syntax Notation One (ASN.1), with capabilities such as converting an EBCDIC-coded text file to an ASCII-coded file, or serialization of objects and other data structures from and to XML. ASN.1 effectively makes an application protocol invariant with respect to syntax.

Layer 7: Application Layer[edit]

The application layer is the OSI layer closest to the end user, which means both the OSI application layer and the user interact directly with the software application. This layer interacts with software applications that implement a communicating component. Such application programs fall outside the scope of the OSI model. Application-layer functions typically include identifying communication partners, determining resource availability, and synchronizing communication. When identifying communication partners, the application layer determines the identity and availability of communication partners for an application with data to transmit. The most important distinction in the application layer is the distinction between the application-entity and the application. For example, a reservation website might have two application-entities: one using HTTP to communicate with its users, and one for a remote database protocol to record reservations. Neither of these protocols have anything to do with reservations. That logic is in the application itself. The application layer has no means to determine the availability of resources in the network.

Cross-layer functions[edit]

Cross-layer functions are services that are not tied to a given layer, but may affect more than one layer.[25] Some orthogonal aspects, such as management and security, involve all of the layers (See ITU-T X.800 Recommendation[26]). These services are aimed at improving the CIA triadconfidentialityintegrity, and availability—of the transmitted data. Cross-layer functions are the norm, in practice, because the availability of a communication service is determined by the interaction between network design and network management protocols.

Specific examples of cross-layer functions include the following:

  • Security service (telecommunication)[26] as defined by ITU-T X.800 recommendation.
  • Management functions, i.e. functions that permit to configure, instantiate, monitor, terminate the communications of two or more entities: there is a specific application-layer protocol, common management information protocol (CMIP) and its corresponding service, common management information service (CMIS), they need to interact with every layer in order to deal with their instances.
  • Multiprotocol Label Switching (MPLS), ATM, and X.25 are 3a protocols. OSI subdivides the Network Layer into three sublayers: 3a) Subnetwork Access, 3b) Subnetwork Dependent Convergence and 3c) Subnetwork Independent Convergence.[27] It was designed to provide a unified data-carrying service for both circuit-based clients and packet-switching clients which provide a datagram-based service model. It can be used to carry many different kinds of traffic, including IP packets, as well as native ATM, SONET, and Ethernet frames. Sometimes one sees reference to a Layer 2.5.
  • Cross MAC and PHY Scheduling is essential in wireless networks because of the time-varying nature of wireless channels. By scheduling packet transmission only in favourable channel conditions, which requires the MAC layer to obtain channel state information from the PHY layer, network throughput can be significantly improved and energy waste can be avoided.[28]

Programming interfaces[edit]

Neither the OSI Reference Model, nor any OSI protocol specifications, outline any programming interfaces, other than deliberately abstract service descriptions. Protocol specifications define a methodology for communication between peers, but the software interfaces are implementation-specific.

For example, the Network Driver Interface Specification (NDIS) and Open Data-Link Interface (ODI) are interfaces between the media (layer 2) and the network protocol (layer 3).

Comparison to other networking suites[edit]

Comparison with TCP/IP model[edit]

The design of protocols in the TCP/IP model of the Internet does not concern itself with strict hierarchical encapsulation and layering.[34] RFC 3439 contains a section entitled “Layering considered harmful“.[35] TCP/IP does recognize four broad layers of functionality which are derived from the operating scope of their contained protocols: the scope of the software application; the host-to-host transport path; the internetworking range; and the scope of the direct links to other nodes on the local network.[36]

Despite using a different concept for layering than the OSI model, these layers are often compared with the OSI layering scheme in the following manner:

  • The Internet application layer maps to the OSI application layer, presentation layer, and most of the session layer.
  • The TCP/IP transport layer maps to the graceful close function of the OSI session layer as well as the OSI transport layer.
  • The internet layer performs functions as those in a subset of the OSI network layer.
  • The link layer corresponds to the OSI data link layer and may include similar functions as the physical layer, as well as some protocols of the OSI’s network layer.

These comparisons are based on the original seven-layer protocol model as defined in ISO 7498, rather than refinements in the internal organization of the network layer.

The OSI protocol suite that was specified as part of the OSI project was considered by many as too complicated and inefficient, and to a large extent unimplementable.[37] Taking the “forklift upgrade” approach to networking, it specified eliminating all existing networking protocols and replacing them at all layers of the stack. This made implementation difficult and was resisted by many vendors and users with significant investments in other network technologies. In addition, the protocols included so many optional features that many vendors’ implementations were not interoperable.[37]

Although the OSI model is often still referenced, the Internet protocol suite has become the standard for networking. TCP/IP’s pragmatic approach to computer networking and to independent implementations of simplified protocols made it a practical methodology.[37] Some protocols and specifications in the OSI stack remain in use, one example being IS-IS, which was specified for OSI as ISO/IEC 10589:2002 and adapted for Internet use with TCP/IP as RFC 1142.

See also[edit]

Uncategorized

Cache coherence

Cache coherence

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An illustration showing multiple caches of some memory, which acts as a shared resource

Incoherent caches: The caches have different values of a single address location.

In computer architecturecache coherence is the uniformity of shared resource data that ends up stored in multiple local caches. When clients in a system maintain caches of a common memory resource, problems may arise with incoherent data, which is particularly the case with CPUs in a multiprocessing system.

In the illustration on the right, consider both the clients have a cached copy of a particular memory block from a previous read. Suppose the client on the bottom updates/changes that memory block, the client on the top could be left with an invalid cache of memory without any notification of the change. Cache coherence is intended to manage such conflicts by maintaining a coherent view of the data values in multiple caches.

Coherent caches: The value in all the caches’ copies is the same.

Overview[edit]

In a shared memory multiprocessor system with a separate cache memory for each processor, it is possible to have many copies of shared data: one copy in the main memory and one in the local cache of each processor that requested it. When one of the copies of data is changed, the other copies must reflect that change. Cache coherence is the discipline which ensures that the changes in the values of shared operands (data) are propagated throughout the system in a timely fashion.[1]

The following are the requirements for cache coherence:[2]

Write Propagation
Changes to the data in any cache must be propagated to other copies (of that cache line) in the peer caches.
Transaction Serialization
Reads/Writes to a single memory location must be seen by all processors in the same order.

Theoretically, coherence can be performed at the load/store granularity. However, in practice it is generally performed at the granularity of cache blocks.[3]

Definition[edit]

Coherence defines the behavior of reads and writes to a single address location.[2]

One type of data occurring simultaneously in different cache memory is called cache coherence, or in some systems, global memory.

In a multiprocessor system, consider that more than one processor has cached a copy of the memory location X. The following conditions are necessary to achieve cache coherence:[4]

  1. In a read made by a processor P to a location X that follows a write by the same processor P to X, with no writes to X by another processor occurring between the write and the read instructions made by P, X must always return the value written by P.
  2. In a read made by a processor P1 to location X that follows a write by another processor P2 to X, with no other writes to X made by any processor occurring between the two accesses and with the read and write being sufficiently separated, X must always return the value written by P2. This condition defines the concept of coherent view of memory. Propagating the writes to the shared memory location ensures that all the caches have a coherent view of the memory. If processor P1 reads the old value of X, even after the write by P2, we can say that the memory is incoherent.

The above conditions satisfy the Write Propagation criteria required for cache coherence. However, they are not sufficient as they do not satisfy the Transaction Serialization condition. To illustrate this better, consider the following example:

A multi-processor system consists of four processors – P1, P2, P3 and P4, all containing cached copies of a shared variable S whose initial value is 0. Processor P1 changes the value of S (in its cached copy) to 10 following which processor P2 changes the value of S in its own cached copy to 20. If we ensure only write propagation, then P3 and P4 will certainly see the changes made to S by P1 and P2. However, P3 may see the change made by P1 after seeing the change made by P2 and hence return 10 on a read to S. P4 on the other hand may see changes made by P1 and P2 in the order in which they are made and hence return 20 on a read to S. The processors P3 and P4 now have an incoherent view of the memory.

Therefore, in order to satisfy Transaction Serialization, and hence achieve Cache Coherence, the following condition along with the previous two mentioned in this section must be met:

  • Writes to the same location must be sequenced. In other words, if location X received two different values A and B, in this order, from any two processors, the processors can never read location X as B and then read it as A. The location X must be seen with values A and B in that order.[5]

The alternative definition of a coherent system is via the definition of sequential consistency memory model: “the cache coherent system must appear to execute all threads’ loads and stores to a single memory location in a total order that respects the program order of each thread”.[3] Thus, the only difference between the cache coherent system and sequentially consistent system is in the number of address locations the definition talks about (single memory location for a cache coherent system, and all memory locations for a sequentially consistent system).

Another definition is: “a multiprocessor is cache consistent if all writes to the same memory location are performed in some sequential order”.[6]

Rarely, but especially in algorithms, coherence can instead refer to the locality of reference. Multiple copies of same data can exist in different cache simultaneously and if processors are allowed to update their own copies freely, an inconsistent view of memory can result.

Coherence mechanisms[edit]

The two most common mechanisms of ensuring coherency are snooping and directory-based, each having their own benefits and drawbacks. Snooping based protocols tend to be faster, if enough bandwidth is available, since all transactions are a request/response seen by all processors. The drawback is that snooping isn’t scalable. Every request must be broadcast to all nodes in a system, meaning that as the system gets larger, the size of the (logical or physical) bus and the bandwidth it provides must grow. Directories, on the other hand, tend to have longer latencies (with a 3 hop request/forward/respond) but use much less bandwidth since messages are point to point and not broadcast. For this reason, many of the larger systems (>64 processors) use this type of cache coherence.

Snooping[edit]

First introduced in 1983,[7] snooping is a process where the individual caches monitor address lines for accesses to memory locations that they have cached.[4] The write-invalidate protocols and write-update protocols make use of this mechanism.
For the snooping mechanism, a snoop filter reduces the snooping traffic by maintaining a plurality of entries, each representing a cache line that may be owned by one or more nodes. When replacement of one of the entries is required, the snoop filter selects for the replacement the entry representing the cache line or lines owned by the fewest nodes, as determined from a presence vector in each of the entries. A temporal or other type of algorithm is used to refine the selection if more than one cache line is owned by the fewest nodes.[8]

Directory-based[edit]

In a directory-based system, the data being shared is placed in a common directory that maintains the coherence between caches. The directory acts as a filter through which the processor must ask permission to load an entry from the primary memory to its cache. When an entry is changed, the directory either updates or invalidates the other caches with that entry.

Distributed shared memory systems mimic these mechanisms in an attempt to maintain consistency between blocks of memory in loosely coupled systems.[9]

Coherence protocols[edit]

Coherence protocols apply cache coherence in multiprocessor systems. The intention is that two clients must never see different values for the same shared data.

The protocol must implement the basic requirements for coherence. It can be tailor-made for the target system or application.

Protocols can also be classified as snoopy or directory-based. Typically, early systems used directory-based protocols where a directory would keep a track of the data being shared and the sharers. In snoopy protocols, the transaction requests (to read, write, or upgrade) are sent out to all processors. All processors snoop the request and respond appropriately.

Write propagation in snoopy protocols can be implemented by either of the following methods:

Write-invalidate
When a write operation is observed to a location that a cache has a copy of, the cache controller invalidates its own copy of the snooped memory location, which forces a read from main memory of the new value on its next access.[4]
Write-update
When a write operation is observed to a location that a cache has a copy of, the cache controller updates its own copy of the snooped memory location with the new data.

If the protocol design states that whenever any copy of the shared data is changed, all the other copies must be “updated” to reflect the change, then it is a write-update protocol. If the design states that a write to a cached copy by any processor requires other processors to discard or invalidate their cached copies, then it is a write-invalidate protocol.

However, scalability is one shortcoming of broadcast protocols.

Various models and protocols have been devised for maintaining coherence, such as MSIMESI (aka Illinois), MOSIMOESIMERSIMESIFwrite-once, Synapse, Berkeley, Firefly and Dragon protocol.[1] In 2011, ARM Ltd proposed the AMBA 4 ACE[10] for handling coherency in SoCs.

See also[edit]

Uncategorized

Sandy Bridge

Sandy Bridge

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Sandy Bridge
General Info
Launched January 9, 2011; 9 years ago
Product code 80623 (desktop)
Performance
Max. CPU clock rate 1.60 GHz to 3.60 GHz
Cache
L1 cache 64 KB per core
L2 cache 256 KB per core
L3 cache 1 MB to 8 MB shared
10 MB to 15 MB (Extreme)
3 MB to 20 MB (Xeon)
Architecture and classification
Architecture Sandy Bridge x86
Instructions MMXAES-NICLMUL
Extensions
Physical specifications
Transistors
  • 504M to 2.27B 32nm
Cores
  • 1–4 (4-6 Extreme, 2-8 Xeon)
GPU(s) HD Graphics
650 MHz to 1100 MHz
HD Graphics 2000
650 MHz to 1250 MHz
HD Graphics 3000
650 MHz to 1350 MHz
HD Graphics P3000
850 MHz to 1350 MHz
Socket(s)
Products, models, variants
Model(s)
  • Celeron Series
    Pentium Series
    Core i3/i5/i7/i7 Extreme Series
    Xeon E3/E5 Series
History
Predecessor Nehalem (Tock)
Westmere (Tick)
Successor Ivy Bridge (Tick)
Haswell (Tock)

Bottom view of a Sandy Bridge i7-2600k

Top of a Sandy Bridge i5

Sandy Bridge is the codename for the microarchitecture used in the “second generation” of the Intel Core processors (Core i7i5i3) – the Sandy Bridge microarchitecture is the successor to Nehalem microarchitecture. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the Core brand.[1][2]

Sandy Bridge is manufactured in the 32 nanometer process and has a soldered contact with the die and IHS (Integrated Heat Spreader), while Intel’s subsequent generation Ivy Bridge (announced 2011) uses a 22 nanometer die shrink and a TIM (Thermal Interface Material) between the die and the IHS. This is known as the tick–tock model.[3]

A Core i7 2600 Sandy Bridge CPU at 3.4 GHz with 1333 MHz DDR3 memory reaches 83 GFLOPS performance in the Whetstone benchmark and 118,000 MIPS in the Dhrystone benchmark.[citation needed]

It is the last Intel microarchitecture for which Windows Vista driver support officially exists.

Technology[edit]

Intel demonstrated a Sandy Bridge processor with A1 stepping at 2 GHz during the Intel Developer Forum in September 2009.[4]

Upgraded features from Nehalem include:

  • Intel Turbo Boost 2.0[5][6][7]
  • 32 KB data + 32 KB instruction L1 cache (4 clocks) and 256 KB L2 cache (11 clocks) per core[8]
  • Shared L3 cache includes the processor graphics (LGA 1155).
  • 64-byte cache line size
  • Improved 3 integer ALU, 2 vector ALU and 2 AGU per core.[9][10]
  • Two load/store operations per CPU cycle for each memory channel
  • Decoded micro-operation cache (uop cache)[11] and enlarged, optimized branch predictor
  • Sandy Bridge retains the four branch predictors found in Nehalem: the branch target buffer (BTB), indirect branch target array, loop detector and renamed return stack buffer (RSB). Sandy Bridge has a single BTB that holds twice as many branch targets as the L1 and L2 BTBs in Nehalem.[12]
  • Improved performance for transcendental mathematicsAES encryption (AES instruction set), and SHA-1 hashing
  • 256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain
  • Advanced Vector Extensions (AVX) 256-bit instruction set with wider vectors, new extensible syntax and rich functionality.[13]
  • Intel Quick Sync Video, hardware support for video encoding and decoding
  • Up to eight physical cores or 16 logical cores through Hyper-threading
  • Integration of the GMCH (integrated graphics and memory controller) and processor into a single die inside the processor package. In contrast, Sandy Bridge’s predecessor, Clarkdale, has two separate dies (one for GMCH, one for processor) within the processor package. This tighter integration reduces memory latency even more.
  • A 14- to 19-stage instruction pipeline, depending on the micro-operation cache hit or miss[14]
Translation lookaside buffer sizes[15][16]
Cache Page Size
Name Level 4 KB 2 MB 1 GB
DTLB 1st 64 32 4
ITLB 1st 128 8 / logical core none
STLB 2nd 512 none none
All translation lookaside buffers (TLBs) are 4-way associative.[17]

Models and steppings[edit]

All Sandy Bridge processors with one, two, or four cores report the same CPUID model 0206A7h[18] and are closely related. The stepping number can not be seen from the CPUID but only from the PCI configuration space. The later Sandy Bridge-E processors with up to eight cores and no graphics are using CPUIDs 0206D6h and 0206D7h.[19] Ivy Bridge CPUs all have CPUID 0306A9h to date, and are built in four different configurations differing in the number of cores, L3 cache and GPU execution units.

Die codename CPUID Step-
ping
Die size
(mm2)
[citation needed]
Transistors
(Millions)
[citation needed]
Cores GPU
EUs
L3
cache
Sockets
Sandy Bridge-HE-4 0206A7h D2 216 1160 4 12 8 MB LGA 1155Socket G2,
BGA-1023BGA-1224
Sandy Bridge-H-2 J1 149 624 2 4 MB LGA 1155Socket G2,
BGA-1023
Sandy Bridge-M-2 Q0 131 504 6 3 MB
Sandy Bridge-EP-8 0206D6h C1 416 2270 8 none 20 MB LGA 2011
0206D7h C2
Sandy Bridge-EP-4 0206D6h M0 270 1270 4 10 MB LGA 2011
0206D7h M1

Performance[edit]

  • The average performance increase, according to IXBT Labs and Semi Accurate as well as many other benchmarking sites, at clock to clock is 11.3% compared to the Nehalem generation, which includes Bloomfield, Clarkdale, and Lynnfield processors.[20]
  • Around twice the integrated graphics performance compared to Clarkdale’s (12 EUs comparison).

List of Sandy Bridge processors[edit]

1Processors featuring Intel’s HD 3000 graphics are set in bold. Other processors feature HD 2000 graphics, HD graphics (Pentium and Celeron models) or no graphics core (Graphics Clock rate indicated by N/A).

  • This list may not contain all the Sandy Bridge processors released by Intel. A more complete listing can be found on Intel’s website.

Desktop platform[edit]

[21] [22] [23]

Target
segment
Processor
Branding & Model
Cores
(Threads)
CPU Clock rate Graphics Clock rate L3
Cache
TDP Release
Date (Y-M-D)
Price
(USD)
Motherboard
Normal Turbo Normal Turbo Socket Interface Memory
Extreme /
High-End
Core i7
Extreme
3970X 6 (12) 3.5 GHz 4.0 GHz N/A 15 MB 150 W 2012-11-12 $999 LGA
2011
DMI 2.0
PCIe 2.0[24]
Up to quad
channel
DDR3-1600[25]
3960X 3.3 GHz 3.9 GHz 130 W 2011-11-14
Core i7 3930K 3.2 GHz 3.8 GHz 12 MB $583
3820 4 (8) 3.6 GHz 10 MB 2012-02-13[26] $294
Performance 2700K 3.5 GHz 3.9 GHz 850 MHz 1350 MHz 8 MB 95 W 2011-10-24 $332 LGA
1155
DMI 2.0
PCIe 2.0
Up to dual
channel
DDR3-1333
2600K 3.4 GHz 3.8 GHz 2011-01-09 $317
2600 $294
2600S 2.8 GHz 65 W $306
Core i5 2550K 4 (4) 3.4 GHz N/A 6 MB 95 W 2012-01-30 $225
2500K 3.3 GHz 3.7 GHz 850 MHz 1100 MHz 2011-01-09 $216
2500 $205
2500S 2.7 GHz 65 W $216
2500T 2.3 GHz 3.3 GHz 650 MHz 1250 MHz 45 W
2450P 3.2 GHz 3.5 GHz N/A 95 W 2012-01-30 $195
2400 3.1 GHz 3.4 GHz 850 MHz 1100 MHz 2011-01-09 $184
2405S 2.5 GHz 3.3 GHz 65 W 2011-05-22 $205
2400S 2011-01-09 $195
2380P 3.1 GHz 3.4 GHz N/A 95 W 2012-01-30 $177
2320 3.0 GHz 3.3 GHz 850 MHz 1100 MHz 2011-09-04
2310 2.9 GHz 3.2 GHz 2011-05-22
2300 2.8 GHz 3.1 GHz 2011-01-09
Mainstream 2390T 2 (4) 2.7 GHz 3.5 GHz 650 MHz 3 MB 35 W 2011-02-20 $195
Core i3 2120T 2.6 GHz N/A 2011-09-04 $127
2100T 2.5 GHz 2011-02-20
2115C 2.0 GHz N/A 25 W 2012-05 $241 BGA
1284
2130 3.4 GHz 850 MHz 1100 MHz 65 W 2011-09-04 $138 LGA
1155
2125 3.3 GHz $134
2120 2011-02-20 $138
2105 3.1 GHz 2011-05-22 $134
2102 Q2 2011 $127
2100 2011-02-20 $117
Pentium G870 2 (2) 2012-06-03 $86
G860 3.0 GHz 2011-09-04
G860T 2.6 GHz 650 MHz 35 W 2012-06-03 $75
G850 2.9 GHz 850 MHz 65 W 2011-05-24 $86
G840 2.8 GHz $75
G645 2.9 GHz 09-03-2012 $64 Up to dual
channel
DDR3-1066
G640 2.8 GHz 06-03-2012
G632 2.7 GHz Q3 2011
G630 2011-09-04 $75
G622 2.6 GHz Q2 2011
G620 2011-05-24 $64
G645T 2.5 GHz 650 MHz 35 W 09-03-2012
G640T 2.4 GHz 06-03-2012
G630T 2.3 GHz 2011-09-04 $70
G620T 2.2 GHz 2011-05-24
Celeron G555 2.7 GHz 850 MHz 1000 MHz 2 MB 65 W 2012-09-02 $52
G550 2.6 GHz 2012-06-03
G540 2.5 GHz 2011-09-04
G530 2.4 GHz $42
G550T 2.2 GHz 650 MHz 35 W 2012-09-02
G540T 2.1 GHz 2012-06-03
G530T 2.0 GHz 2011-09-04 $47
G470 1 (2) 1.5 MB 2013-06-09 $37 Up to dual
channel
DDR3-1333
G465 1.9 GHz 2012-09-02 Up to dual
channel
DDR3-1066
G460 1.8 GHz 2011-12-11
G440 1 (1) 1.6 GHz 1 MB 2011-09-04

Suffixes to denote:

  • K – Unlocked (adjustable CPU ratio up to 57 bins)
  • P – Versions clocked slightly higher than similar models, but with onboard-graphics deactivated.
  • S – Performance-optimized lifestyle (low power with 65W TDP)
  • T – Power-optimized lifestyle (ultra low power with 35-45W TDP)
  • X – Extreme performance (adjustable CPU ratio with no ratio limit)

NOTE3970X3960X3930K, and 3820 are actually of Sandy Bridge-E edition.

Server platform[edit]

Target
Segment
Socket Processor
Branding & Model
Cores
(Threads)
CPU Clock rate Graphics Clock rate L3
Cache
Interface Supported
Memory
TDP Release
Date
Price
(USD)
Standard Turbo Normal Turbo
4P Server LGA
2011
Xeon E5 4650 8 (16) 2.7 GHz 3.3 GHz N/A 20 MB 2× QPI
DMI 2.0
PCIe 3.0
4x DDR3-1600 130 W 2012-05-14 $3616
4650L 2.6 GHz 3.1 GHz 115 W
4640 2.4 GHz 2.8 GHz 95 W $2725
4620 2.2 GHz 2.6 GHz 16 MB 4x DDR3-1333 $1611
4617 6 (6) 2.9 GHz 3.4 GHz 15 MB 4x DDR3-1600 130 W
4610 6 (12) 2.4 GHz 2.9 GHz 4x DDR3-1333 95 W $1219
4607 2.2 GHz N/A 12 MB 4x DDR3-1066 $885
4603 4 (8) 2.0 GHz 10 MB $551
2P Server 2687W 8 (16) 3.1 GHz 3.8 GHz 20 MB 4x DDR3-1600 150 W 2012-03-06 $1885
2690 2.9 GHz 135 W $2057
2680 2.7 GHz 3.5 GHz 130 W $1723
2689 2.6 GHz 3.6 GHz 115 W OEM
2670 3.3 GHz $1552
2665 2.4 GHz 3.1 GHz $1440
2660 2.2 GHz 3.0 GHz 95 W $1329
2658 2.1 GHz 2.4 GHz $1186
2650 2.0 GHz 2.8 GHz $1107
2650L 1.8 GHz 2.3 GHz 70 W
2648L 2.1 GHz $1186
2667 6 (12) 2.9 GHz 3.5 GHz 15 MB 130 W $1552
2640 2.5 GHz 3.0 GHz 4x DDR3-1333 95 W $884
2630 2.3 GHz 2.8 GHz $612
2620 2.0 GHz 2.5 GHz $406
2630L 60 W $662
2628L 1.8 GHz N/A ? OEM
2643 4 (8) 3.3 GHz 3.5 GHz 10 MB 4x DDR3-1600 130 W 2012-03-06 $884
2618L 1.8 GHz N/A 4x DDR3-1066 50 W ? OEM
2609 4 (4) 2.4 GHz 80 W 2012-03-06 $246
2603 1.8 GHz $202
2637 2 (4) 3.0 GHz 3.5 GHz 5 MB 4x DDR3-1600 $884
LGA
1356
2470 8 (16) 2.3 GHz 3.1 GHz 20 MB 1× QPI
DMI 2.0
PCIe 3.0
3x DDR3-1600 95 W 2012-05-14 $1440
2450 2.1 GHz 2.9 GHz $1106
2450L 1.8 GHz 2.3 GHz 70 W
2448L 2.1 GHz $1151
2449L 1.4 GHz 1.8 GHz 50 W OEM
2440 6 (12) 2.4 GHz 2.9 GHz 15 MB 3x DDR3-1333 95 W $834
2430 2.2 GHz 2.7 GHz $551
2420 1.9 GHz 2.4 GHz $388
2430L 2.0 GHz 2.5 GHz 60 W $662
2428L 1.8 GHz 2.0 GHz $628
2418L 4 (8) 2.0 GHz 2.1 GHz 10 MB 50 W $387
2407 4 (4) 2.2 GHz N/A 3x DDR3-1066 80 W $250
2403 1.8 GHz $192
1P Server LGA
2011
1660 6 (12) 3.3 GHz 3.9 GHz 15 MB 2× QPI
DMI 2.0
PCIe 3.0
Up to quad
channel
DDR3-1600
130 W 2012-03-06 $1080
1650 3.2 GHz 3.8 GHz 12 MB $583
1620 4 (8) 3.6 GHz 10 MB $294
1607 4 (4) 3.0 GHz N/A Up to quad
channel
DDR3-1066
$244
1603 2.8 GHz $198
LGA
1356
1428L 6 (12) 1.8 GHz N/A 15 MB 1× QPI
DMI 2.0
PCIe 3.0
3x DDR3-1333 60 W Q2 2012 $395
1410 4 (8) 2.8 GHz 3.2 GHz 10 MB 80 W 2012-05-14
Pentium 1407 2 (2) N/A 5 MB 3x DDR3-1066
1405 1.2 GHz 1.8 GHz 40 W August 2012 $143
1403 2.6 GHz N/A 80 W 2012-05-14
LGA
1155
Xeon E3 1290 4 (8) 3.6 GHz 4.0 GHz 8 MB DMI 2.0
PCIe 2.0
Up to dual
channel
DDR3-1333
95 W 2011-05-29 $885
1280 3.5 GHz 3.9 GHz 2011-04-03 $612
1275 3.4 GHz 3.8 GHz 850 MHz 1350 MHz $339
1270 N/A 80 W $328
1260L 2.4 GHz 3.3 GHz 650 MHz 1250 MHz 45 W $294
1245 3.3 GHz 3.7 GHz 850 MHz 1350 MHz 95 W $262
1240 N/A 80 W $250
1235 3.2 GHz 3.6 GHz 850 MHz 1350 MHz 95 W $240
1230 N/A 80 W $215
1225 4 (4) 3.1 GHz 3.4 GHz 850 MHz 1350 MHz 6 MB 95 W $194
1220 N/A 8 MB 80 W $189
1220L 2 (4) 2.2 GHz 3 MB 20 W
BGA
1284
1125C 4 (8) 2.0 GHz N/A 8 MB Up to dual
channel
DDR3-1600
40 W May 2012 $444
1105C 1.0 GHz 6 MB 25 W $333
LGA
1155
Pentium 350 2 (4) 1.2 GHz 3 MB Up to dual
channel
DDR3-1333
15 W November 2011 $159

Mobile platform[edit]

  • Core i5-2515E and Core i7-2715QE processors have support for ECC memory and PCI express port bifurcation.
  • All mobile processors, except Celeron and Pentium, use Intel’s Graphics subsystem HD 3000 (12 EUs).
Target
Segment
Processor
Branding & Model
Cores /
Threads
CPU Clock rate Graphics Clock rate L3
Cache
TDP Release
Date
Price
(USD)
Motherboard
Normal Turbo
(1C/2C/4C)
Normal Turbo Interface Socket
Extreme Core i7
Extreme
2960XM 4 (8) 2.7 GHz 3.7/3.6/3.4 GHz 650 MHz 1300 MHz 8 MB 55 W 2011-09-04 $1096 *DMI 2.0
*Memory: Up to
dual channel
DDR3-1600 MHz
*PCIe 2.0
Socket G2 /
BGA-1224 (in embedded products)[27]
2920XM 2.5 GHz 3.5/3.4/3.2 GHz 2011-01-05
Performance Core i7 2860QM 2.5 GHz 3.6/3.5/3.3 GHz 45 W 2011-09-04 $568
2820QM 2.3 GHz 3.4/3.3/3.1 GHz 2011-01-05
2760QM 2.4 GHz 3.5/3.4/3.2 GHz 6 MB 2011-09-04 $378
2720QM 2.2 GHz 3.3/3.2/3.0 GHz 2011-01-05
2715QE 2.1 GHz 3.0/2.9/2.7 GHz 1200 MHz
2710QE
2675QM 2.2 GHz 3.1/3.0/2.8 GHz 1200 MHz 2011-10-02 *DMI 2.0
*Memory: Up to
dual channel
DDR3-1333 MHz
*PCIe 2.0
2670QM 1100 MHz
2635QM 2.0 GHz 2.9/2.8/2.6 GHz 1200 MHz 2011-01-05
2630QM 1100 MHz
Mainstream 2640M 2 (4) 2.8 GHz 3.5/3.3 GHz 1300 MHz 4 MB 35 W 2011-09-04 $346 Socket G2 /
BGA-1023 (in embedded products)[27]
2620M 2.7 GHz 3.4/3.2 GHz 2011-02-20
2649M 2.3 GHz 3.2/2.9 GHz 500 MHz 1100 MHz 25 W
2629M 2.1 GHz 3.0/2.7 GHz $311
2655LE 2.2 GHz 2.9/2.7 GHz 650 MHz 1000 MHz $346
2677M 1.8 GHz 2.9/2.6 GHz 350 MHz 1200 MHz 17 W 2011-06-20 $317
2637M 1.7 GHz 2.8/2.5 GHz $289
2657M 1.6 GHz 2.7/2.4 GHz 1000 MHz 2011-02-20 $317
2617M 1.5 GHz 2.6/2.3 GHz 950 MHz $289
2610UE 2.4/2.1 GHz 850 MHz $317
Core i5 2557M 1.7 GHz 2.7/2.4 GHz 1200 MHz 3 MB 2011-06-20 $250
2537M 1.4 GHz 2.3/2.0 GHz 900 MHz 2011-02-20
2467M 1.6 GHz 2.3/2.0 GHz 1150 MHz 2011-06-19
2540M 2.6 GHz 3.3/3.1 GHz 650 MHz 1300 MHz 35 W 2011-06-20 $266
2520M 2.5 GHz 3.2/3.0 GHz $225
2515E 3.1/2.8 GHz 1100 MHz $266
2510E
2450M 1300 MHz 2012-01 $225
2435M 2.4 GHz 3.0/2.7 GHz 2011-10-02 OEM
2430M 1200 MHz $225
2410M 2.3 GHz 2.9/2.6 GHz 2011-06-20
Core i3 2370M 2.4 GHz N/A 1150 MHz 2012-01
2350M 2.3 GHz 2011-10-02
2348M 2013-01 OEM
2330E 2.2 GHz 1050 MHz 2011-06-19 $225
2330M 1100 MHz
2328M 2012-09
2312M 2.1 GHz Q2 2011 OEM
2310E 1050 MHz 2011-02-20
2310M 1100 MHz
2377M 1.5 GHz 350 MHz 1000 MHz 17 W Q3 2012 $225
2375M 2012-03
2367M 1.4 GHz 2011-10-02 $250
2365M 2012-09 $225
2357M 1.3 GHz 950 MHz 2011-06-19 OEM
2340UE 800 MHz $250
Pentium B915C 1.5 GHz N/A 15 W 2012-05 $138
997 2 (2) 1.6 GHz 350 MHz 1000 MHz 2 MB 17 W 2012-09-30 $134
987 1.5 GHz Q3 2012
977 1.4 GHz 2012-01
967 1.3 GHz 2011-10-02
957 1.2 GHz 800 MHz 2011-06-19
B980 2.4 GHz 650 MHz 1150 MHz 35 W 2012-09 $125
B970 2.3 GHz 2012-01
B960 2.2 GHz 1100 MHz 2011-10-02 $134
B950 2.1 GHz 2011-06-19
B940 2.0 GHz
Celeron B840 1.9 GHz 1000 MHz 2011-09-04 $86
B830 1.8 GHz 1050 MHz 2012-09-30
B820[28] 1.7 GHz 2012-07-29
B815[29] 1.6 GHz 2012-01
B810E 1000 MHz 2011-06-19
B810 950 MHz 2011-03-13
B800 1.5 GHz 1000 MHz 2011-06-19 $80
887 350 MHz 17 W 09-30-2012 $86
877 1.4 GHz 2012-07-29
867 1.3 GHz January 2012 $134
857 1.2 GHz 2011-07-03
847 1.1 GHz 800 MHz 2011-06-19
847E
807 1 (2) 1.5 GHz 950 MHz 1.5 MB 2012-07-29 $70
725C 1.3 GHz N/A 10 W 2012-05 $74
827E 1 (1) 1.4 GHz 350 MHz 800 MHz 17 W 2011-07-03 $107
797 950 MHz 2012-01
787 1.3 GHz 2011-07-03
B730 1.8 GHz 650 MHz 1000 MHz 35 W 2012-07-29 $70
B720[30] 1.7 GHz 2012-01
B710 1.6 GHz 2011-06-19
807UE 1.0 GHz 350 MHz 800 MHz 1 MB 10 W 2011-11 $117

Suffixes to denote:

  • M – Mobile processors
    • XM – Unlocked
    • QM – Quad-core
  • E – Embedded mobile processors
    • QE – Quad-core
    • LE – Performance-optimized
    • UE – Power-optimized

Cougar Point chipset flaw[edit]

On 31 January 2011, Intel issued a recall on all 67-series motherboards due to a flaw in the Cougar Point Chipset.[31] A hardware problem exists, in which the chipset’s SATA II ports may fail over time, causing failure of connection to SATA devices, though data is not at risk.[32] Intel claims that this problem will affect only 5% of users over 3 years; however, heavier I/O workloads can exacerbate the problem.

Intel stopped production of flawed B2 stepping chipsets and began producing B3 stepping chipsets with the silicon fix. Shipping of these new chipsets started on 14 February 2011 and Intel estimated full recovery volume in April 2011.[33] Motherboard manufacturers (such as ASUS and Gigabyte Technology) and computer manufacturers (such as Dell and Hewlett-Packard) stopped selling products that involved the flawed chipset and offered support for affected customers. Options ranged from swapping for B3 motherboards to product refunds.[34][35]

Sandy Bridge processor sales were temporarily on hold, as one cannot use the CPU without a motherboard. However, processor release dates were not affected.[36] After two weeks, Intel continued shipping some chipsets, but manufacturers had to agree to a set of terms that will prevent customers from encountering the bug.[37]

Identifying chipset version[edit]

BIOS[edit]

Motherboard manufacturer websites should have instruction about how to identify chipset stepping version using bios.

Linux[edit]

lshw produces this partial output :

*-isa
             description: ISA bridge
             product: H61 Express Chipset Family LPC Controller
             vendor: Intel Corporation
             physical id: 1f
             bus info: pci@0000:00:1f.0
             version: 05
             width: 32 bits
             clock: 33MHz
             capabilities: isa bus_master cap_list
             configuration: driver=lpc_ich latency=0
             resources: irq:0

above output says ‘version: 05’. Intel 6 Series Chipset and Intel C200 Series Chipset Specification Update from google (intel h61 revision 05) result 1 under ‘pch device and revision identification’ page 13, says ’05h’ is located under ‘b3 rev id’ so ‘b3’ is the chipset stepping version. Suffix “h” means hexadecimal so ’05h’ means 5.

Limitations[edit]

Overclocking[edit]

With Sandy Bridge, Intel has tied the speed of every bus (USB, SATA, PCI, PCI-E, CPU cores, Uncore, memory etc.) to a single internal clock generator issuing the basic 100 MHz Base Clock (BClk).[38] With CPUs being multiplier locked, the only way to overclock is to increase the BClk, which can be raised by only 5–7% without other hardware components failing. As a work around, Intel made available K/X-series processors, which feature unlocked multipliers; with a multiplier cap of 57 for Sandy Bridge.[39] For the Sandy Bridge E platform, there is alternative method known as the BClk ratio overclock.[40]

During IDF (Intel Developer Forum) 2010, Intel demonstrated an unknown Sandy Bridge CPU running stably overclocked at 4.9 GHz on air cooling.[41][42]

Chipset[edit]

Non-K edition CPUs can overclock up to four bins from its turbo multiplier. Refer here for chipset support.

vPro remote-control[edit]

Sandy and Ivy Bridge processors with vPro capability have security features that can remotely disable a PC or erase information from hard drives. This can be useful in the case of a lost or stolen PC. The commands can be received through 3G signals, Ethernet, or Internet connections. AES encryption acceleration will be available, which can be useful for video conferencing and VoIP applications.[43][44]

Intel Insider[edit]

Sandy and Ivy Bridge processors contain a DRM technology that some video streaming web sites rely on to restrict use of their content. Such web sites offer 1080p streaming to users with such CPUs and downgrade the quality for other users.[45]

Software development kit[edit]

With the introduction of the Sandy Bridge microarchitecture, Intel also introduced the Intel Data Plane Development Kit (Intel DPDK) to help developers of communications applications take advantage of the platform in packet processing applications, and network processors.[46]

Roadmap[edit]

Intel demonstrated the Haswell architecture in September 2011, released in 2013 as the successor to Sandy Bridge and Ivy Bridge with general availability in 2014.[47]

See also[edit]

Uncategorized

Northbridge (computing)

Northbridge (computing)

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A typical north/southbridge layout

A typical north/southbridge layout

northbridge or host bridge is one of the two chips in the core logic chipset architecture on a PC motherboard, the other being the southbridge. Unlike the southbridge, northbridge is connected directly to the CPU via the front-side bus (FSB) and is thus responsible for tasks that require the highest performance. The northbridge, also known as Memory Controller Hub, is usually paired with a southbridge.[1] In systems where they are included, these two chips manage communications between the CPU and other parts of the motherboard, and constitute the core logic chipset of the PC motherboard.[2]

On older Intel based PCs, the northbridge was also named external memory controller hub (MCH) or graphics and memory controller hub (GMCH) if equipped with integrated graphics. Increasingly these functions became integrated into the CPU chip itself,[3] beginning with memory and graphics controllers. For Intel Sandy Bridge and AMD Accelerated Processing Unit processors introduced in 2011, all of the functions of the northbridge reside on the CPU,[4] while AMD FX CPUs still require external northbridge and southbridge chips.

Separating the different functions into the CPU, northbridge, and southbridge chips was due to the difficulty of integrating all components onto a single chip.[5] In some instances, the northbridge and southbridge functions have been combined onto one die when design complexity and fabrication processes permitted it; for example, the Nvidia GeForce 320M in the 2010 MacBook Air is a northbridge/southbridge/GPU combo chip.[6]

As CPU speeds increased over time, a bottleneck eventually emerged between the processor and the motherboard, due to limitations caused by data transmission between the CPU and its support chipset.[7] Accordingly, starting with the AMD Athlon64 series CPUs (based on the Opteron), a new architecture was used where some functions of the north- and southbridge chips were moved to the CPU. Modern Intel Core processors have the northbridge integrated on the CPU die, where it is known as the uncore or system agent.

Overview[edit]

The northbridge typically handles communications among the CPU, in some cases RAM, and PCI Express (or AGP) video cards, and the southbridge.[8][9] Some northbridges also contain integrated video controllers, also known as a Graphics and Memory Controller Hub (GMCH) in Intel systems. Because different processors and RAM require different signaling, a given northbridge will typically work with only one or two classes of CPUs and generally only one type of RAM.

There are a few chipsets that support two types of RAM (generally these are available when there is a shift to a new standard). For example, the northbridge from the Nvidia nForce2 chipset will only work with Socket A processors combined with DDR SDRAM; the Intel i875 chipset will only work with systems using Pentium 4 processors or Celeron processors that have a clock speed greater than 1.3 GHz and utilize DDR SDRAM, and the Intel i915g chipset only works with the Intel Pentium 4 and the Celeron, but it can use DDR or DDR2 memory.

Etymology[edit]

The name is derived from drawing the architecture in the fashion of a map. The CPU would be at the top of the map comparable to due north on most general purpose geographical maps. The CPU would be connected to the chipset via a fast bridge (the northbridge) located north of other system devices as drawn. The northbridge would then be connected to the rest of the chipset via a slow bridge (the southbridge) located south of other system devices as drawn.

Intel i815EP northbridge

Overclocking[edit]

The northbridge plays an important part in how far a computer can be overclocked, as its frequency is commonly used as a baseline for the CPU to establish its own operating frequency. This chip typically gets hotter as processor speed becomes faster, requiring more cooling. There is a limit to CPU overclocking, as digital circuits are limited by physical factors such as rise, fall, delay and storage times of the transistors, current gain bandwidth product, parasitic capacitance, and propagation delay, which increases with (among other factors) operating temperature; consequently most overclocking applications have software-imposed limits on the multiplier and external clock setting. Additionally, heat is a major limiting factor, as higher voltages are needed to properly activate field effect transistors inside CPUs and this higher voltage produces larger amounts of heat, requiring greater thermal solutions on the die.

Evolution[edit]

A part of an IBM T42 laptop motherboard.

The overall trend in processor design has been to integrate more functions onto fewer components, which decreases overall motherboard cost and improves performance. The memory controller, which handles communication between the CPU and RAM, was moved onto the processor die by AMD beginning with their AMD64 processors and by Intel with their Nehalem processors. One of the advantages of having the memory controller integrated on the CPU die is to reduce latency from the CPU to memory.

Another example of this kind of change is Nvidia‘s nForce3 for AMD64 systems. It combines all of the features of a normal southbridge with an Accelerated Graphics Port (AGP) port and connects directly to the CPU. On nForce4 boards it was marketed as a media communications processor (MCP).

AMD Accelerated Processing Unit processors feature full integration of northbridge functions onto the CPU chip, along with processor cores, memory controller and graphics processing unit (GPU). This was an evolution of the AMD64, since the memory controller was integrated on the CPU die in the AMD64.

The northbridge was replaced by the system agent introduced by the Sandy Bridge microarchitecture in 2011, which essentially handles all previous Northbridge functions.[10] Intel’s Sandy Bridge processors feature full integration of northbridge functions onto the CPU chip, along with processor cores, memory controller and graphics processing unit (GPU). This was a further evolution of the Westmere architecture, which also featured a CPU and GPU in the same package.[11]

See also[edit]

Uncategorized

Direct Media Interface

Direct Media Interface

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In computingDirect Media Interface (DMI) is Intel‘s proprietary link between the northbridge and southbridge on a computer motherboard. It was first used between the 9xx chipsets and the ICH6, released in 2004. Previous Intel chipsets had used the Hub Interface to perform the same function, and server chipsets use a similar interface called Enterprise Southbridge Interface (ESI).[1] While the “DMI” name dates back to ICH6, Intel mandates specific combinations of compatible devices, so the presence of a DMI interface does not guarantee by itself that a particular northbridge–southbridge combination is allowed.

DMI shares many characteristics with PCI Express, using multiple lanes and differential signaling to form a point-to-point link. Most implementations use a ×4 link, while some mobile systems (e.g. 915GMS, 945GMS/GSE/GU and the Atom N450) use a ×2 link, halving the bandwidth. The original implementation provides 10 Gbit/s (1 GB/s) in each direction using a ×4 link.

DMI 2.0, introduced in 2011, doubles the data transfer rate to 2 GB/s with a ×4 link. It is used to link an Intel CPU with the Intel Platform Controller Hub (PCH), which supersedes the historic implementation of a separate northbridge and southbridge.[2]:14

DMI 3.0, released in August 2015, allows the 8 GT/s transfer rate per lane, for a total of four lanes and 3.93 GB/s for the CPU–PCH link. It is used by two-chip variants of the Intel Skylake microprocessors, which are used in conjunction with Intel 100 Series chipsets;[3][4] some low power (Skylake-U onwards) and ultra low power (Skylake-Y onwards) mobile Intel processors have the PCH integrated into the physical package as a separate die, referred to as OPI (On Package DMI interconnect Interface)[5] and effectively following the system on a chip (SoC) design layout.[6] On 9 March 2015, Intel announced the Broadwell-based Xeon D as its first enterprise platform to fully incorporate the PCH in an SoC configuration.[7]

Implementations[edit]

Northbridge devices supporting a northbridge DMI are the Intel 915-series, 925-series, 945-series, 955-series, 965-series, 975-series, G31/33, P35X38X48P45 and X58[citation needed].

Processors supporting a northbridge DMI and, therefore, not using a separate northbridge, are the Intel AtomIntel Core i3Intel Core i5, and Intel Core i7 (8xx, 7xx and 6xx, but not 9xx). Processors supporting a northbridge DMI 2.0 and, therefore not using a separate northbridge, are the 2000, 3000, 4000, and 5000 series of the Intel Core i3Core i5 and Core i7.

Southbridge devices supporting a southbridge DMI are the ICH6, ICH7, ICH8, ICH9, ICH10, NM10, P55, H55, H57, Q57, PM55, HM55, HM57, QM57 and QS57[citation needed].

PCH devices supporting DMI 2.0 are the Intel B65, H61, H67, P67, Q65, Q67, Z68, HM65, HM67, QM67, QS67, B75, H77, Q75, Q77, Z75, Z77, X79, HM75, HM76, HM77, QM77, QS77, UM77, H81, B85, Q85, Q87, H87, Z87, H97, Z97, C222, C224, C226X99, H110[8], and H310.[9]

PCH devices supporting DMI 3.0 are the Intel Z170, H170, HM170, Q170, QM170, Q150, B150, C236, CM236, C232, and C620. [10][11][12][13][14][15][16][17][18][19] The Intel 200 series, B360[20], H370[21], Q370[22], Z370[23] and Intel 400 series chipsets also support DMI 3.0.

See also[edit]

Uncategorized

Westmere (microarchitecture)

Westmere (microarchitecture)

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Westmere
General Info
Launched January 7, 2010; 10 years ago
Performance
Max. CPU clock rate 1.06 GHz to 3.46 GHz
Cache
L1 cache 64 KB per core
L2 cache 256 KB per core
L3 cache 4 MB to 30 MB shared
Architecture and classification
Architecture Nehalem x86
Instructions MMXAES-NICLMUL
Extensions
Physical specifications
Transistors
  • 382M to 2600M 32nm
Cores
  • 2-6 (4-10 Xeon)
GPU(s) 533 MHz to 900 MHz
177M 45nm (K0)
Socket(s)
Products, models, variants
Model(s)
  • Core in, Xeon
History
Predecessor Nehalem
Successor Sandy Bridge

Connection of the GPU inside the Westmere microarchitecture

Westmere (formerly Nehalem-C) is the code name given to the 32 nm die shrink of Nehalem. While sharing the same CPU sockets, Westmere included Intel HD Graphics, while Nehalem did not.

The first Westmere-based processors were launched on January 7, 2010, by Intel Corporation.

The Westmere architecture has been available under the Intel brands of Core i3Core i5Core i7PentiumCeleron and Xeon.

Technology[edit]

Westmere’s feature improvements from Nehalem, as reported:

Translation lookaside buffer sizes [5]
Cache Page Size
Name Level 4 KB 2 MB 1 GB
DTLB 1st 64 32 N/A
ITLB 1st 128 7 / logical core N/A
STLB 2nd 512 none none

CPU variants[edit]

Processing Cores
(Interface)
Process Die Size CPUID Model Stepping Mobile Desktop,
UP Server
DP Server MP Server
Ten-Core
(Quad-channel)[6]
32 nm 513 mm² 206F2 47 A2 Westmere-EX
(80615)
Six-Core
(Triple-Channel)
32 nm 248 mm² 206C0 (ES/QS),
206C1 (ES/QS),
206C2
44 A0,
B0,
B1
Gulftown
(80613)
Westmere-EP
(80614)
Dual-Core (Dual-Channel,
PCIe, Graphics Core)
32 nm
45 nm
114 mm²
+81 mm²
20652
20655
37 C2
K0
Arrandale
(80617)
Clarkdale
(80616)

Westmere CPUs[edit]

  • TDP includes the integrated GPU, if present.
  • Clarkdale processors feature 16 PCIe 2.0 lanes, which can be used in 1×16 or 2×8 configuration.
  • Clarkdale and Arrandale contain the 32 nm dual core processor Hillel and the 45 nm integrated graphics device Ironlake, and support switchable graphics.[7][8]
  • Only certain higher-end CPUs support AES-NI and 1GB Huge Pages.

Server / Desktop processors[edit]

Codename Market Cores /
Threads
Socket Processor
Branding & model
Clock rate Turbo TDP Interfaces L3
cache
Release
Date
Price
Core GPU Chipset Memory
Westmere-EX[9] MP Server 10 (20) LGA
1567
Xeon E7-8870 2.4 GHz N/A Yes 130 W 4× QPI 6.4 GT/s 4× DDR3-1066 30 MB 2011-04-05[10] $4616
E7-4870 $4394
E7-2870 $4227
E7-8867L 2.13 GHz 105 W $4172
E7-8860 2.26 GHz 130 W 24 MB $4061
E7-4860 $3838
E7-2860 $3670
E7-8850 2 GHz $3059
E7-4850 $2837
E7-2850 $2558
8 (8) E7-8837 2.66 GHz $2280
8 (16) E7-8830 2.13 GHz 105 W
E7-4830 $2059
E7-2830 $1779
E7-4820 2 GHz 4× QPI 5.86 GT/s 18 MB $1446
E7-2820 $1334
6 (12) E7-4807 1.86 GHz No 95 W 4× QPI 4.8 GT/s 4× DDR3-800 $890
E7-2803 1.73 GHz 105 W $774
Gulftown /
Westmere-EP
[11]
DP Server 2 (4) LGA
1366
Xeon X5698[12] 4.4 GHz N/A No 130 W 2× QPI 6.4 GT/s 3× DDR3-1333 12 MB Q1 2011 OEM
6 (12) X5690 3.46 GHz Yes 2011-02-13 $1663
X5680 3.33 GHz 2010-03-16
X5679 3.2 GHz 115 W 2011-02-13 OEM
X5675 3.06 GHz 95 W $1440
X5670 2.93 GHz 2010-03-16
X5660 2.8 GHz $1219
X5650 2.66 GHz $996
E5649 2.53 GHz 80 W 2× QPI 5.86 GT/s 2011-02-13 $774
E5645 2.4 GHz 2010-03-16 $551
L5645 60 W 2011-02-13 OEM
L5640 2.26 GHz 2010-03-16 $996
L5639 2.13 GHz 2011-02-13 OEM
L5638 2.0 GHz 2010-03-16 $958
4 (8) X5687 3.6 GHz 130 W 2× QPI 6.4 GT/s 2011-02-13 $1663
X5677 3.46 GHz 2010-03-16
X5672 3.2 GHz 95 W 2011-02-13 $1440
X5667 3.06 GHz 2010-03-16
X5647 2.93 GHz 130 W 2× QPI 5.86 GT/s 3× DDR3-1066 2011-02-13 $774
E5640 2.66 GHz 80 W 2010-03-16
E5630 2.53 GHz $551
E5620 2.4 GHz $387
L5630 2.13 GHz 40 W $551
L5618 1.86 GHz $530
4 (4) L5609 1.86 GHz No 2× QPI 4.8 GT/s $440
E5607 2.26 GHz 80 W 8 MB 2011-02-13 $276
E5606 2.13 GHz $219
E5603 1.6 GHz 4 MB $188
UP Server 6 (12) Xeon W3690 3.46 GHz N/A Yes 130 W 1× QPI 6.4 GT/s 3× DDR3-1333 12 MB 2011-02-13[13] $999
W3680 3.33 GHz 2010-03-16[14] $999
W3670 3.20 GHz 1× QPI 4.8 GT/s 3× DDR3-1066 2010-08-29 $885
Extreme /
Performance
Desktop
Core i7
Extreme
990X 3.46 GHz 1× QPI 6.4 GT/s 2011-02-13 $999
980X 3.33 GHz 2010-03-16
Core i7 980 1× QPI 4.8 GT/s 2011-06-26 $583
970 3.20 GHz 2010-07-17 $583
Clarkdale[15] UP Server 2 (4) LGA
1156
Xeon L3406 2.26 GHz N/A Yes 30 W DMI 2× DDR3-1066 4 MB 2010-03-16 $189
2 (2) L3403 2.0 GHz 2010-10 $
Mainstream /
Value
Desktop
2 (4) Core i5 680 3.6 GHz 733 MHz 73 W 2× DDR3-1333 2010-04-18 $294
670 3.46 GHz 2010-01-07 $284
661 3.33 GHz 900 MHz 87 W $196
660 733 MHz 73 W
655K 3.2 GHz 2010-05-30 $216
650 2010-01-07 $176
Core i3 560 3.33 GHz No 2010-08-29 $138
550 3.20 GHz 2010-05-30
540 3.06 GHz 2010-01-07 $133
530 2.93 GHz $113
2 (2) Pentium G6960 533 MHz 2× DDR3-1066 3 MB 2011-01-09 $89
G6951 2.8 GHz Q3 2010 OEM
G6950 2010-01-07 $87
Celeron G1101 2.26 GHz 2 MB $70
Codename Market Cores /
Threads
Socket Processor
Branding & model
Core GPU Turbo TDP Chipset Memory L3
cache
Release
Date
Price
Clock rate Interfaces

Mobile processors[edit]

Codename Market Cores /
Threads
Processor
Branding & Model
CPU Clock rate GPU Clock rate Turbo TDP Memory L3
cache
Interface Release
Date
Price
Standard Turbo
(1C/2C active cores )
Arrandale Mainstream /Value Mobile 2 (4) Core i7 640M 2.8 GHz 3.46/3.2 GHz 766 MHz Yes 35 W 2× DDR3-1066 4 MB * DMI
PCIe 1 x16
* Socket:
µPGA-988 /
BGA-1288
2010-09-26 $346
620M 2.66 GHz 3.33/3.06 GHz 2010-01-07 $332
610E 2.53 GHz 3.2/2.93 GHz
660LM 2.26 GHz 3.06/2.8 GHz 566 MHz 25 W 2010-09-26 $346
640LM 2.13 GHz 2.93/2.66 GHz 2010-01-07 $332
620LM / 620LE 2.0 GHz 2.8/2.53 GHz $300
680UM 1.46 GHz 2.53/2.16 GHz 500 MHz 18 W 2× DDR3-800 2010-09-26 $317
660UM / 660UE 1.33 GHz 2.4/2.0 GHz 2010-05-25
640UM 1.2 GHz 2.26/1.86 GHz 2010-01-07 $305
620UM / 620UE 1.06 GHz 2.13/1.76 GHz $278
Core i5 580M 2.66 GHz 3.33/2.93 GHz 766 MHz 35 W 2× DDR3-1066 3 MB 2010-09-26 $266
560M 3.2/2.93 GHz $225
540M 2.53 GHz 3.06/2.8 GHz 2010-01-07 $257
520M / 520E 2.4 GHz 2.93/2.66 GHz $225
560UM 1.33 GHz 2.13/1.86 GHz 500 MHz 18 W 2× DDR3-800 2010-09-26 $250
540UM 1.2 GHz 2.0/1.73 GHz 2010-05-25
520UM 1.06 GHz 1.86/1.6 GHz 2010-01-07 $241
480M 2.66 GHz 2.93/2.93 GHz 766 MHz 35 W 2× DDR3-1066 2011-01-09 OEM
460M 2.53 GHz 2.8/2.8 GHz 2010-09-26
450M 2.4 GHz 2.66/2.66 GHz 2010-06-26
430M 2.26 GHz 2.53/2.53 GHz 2010-01-07
470UM 1.33 GHz 1.86/1.6 GHz 500 MHz 18 W 2× DDR3-800 2010-10-01
430UM 1.2 GHz 1.73/1.46 GHz 2010-05-25
Core i3 390M 2.66 GHz n/a 667 MHz No 35 W 2× DDR3-1066 2011-01-09
380M 2.53 GHz 2010-09-26
370M 2.4 GHz 2010-06-20
350M 2.26 GHz 2010-01-07
330M / 330E 2.13 GHz
380UM 1.33 GHz 500 MHz 18 W 2× DDR3-800 2010-10-01
330UM 1.2 GHz 2010-05-25
2 (2) Pentium P6300 2.26 GHz 667 MHz 35 W 2× DDR3-1066 2011-01-09
P6200 2.13 GHz 2010-09-26
P6100 2.0 GHz
P6000 1.86 GHz 2010-06-20
U5600 1.33 GHz 500 MHz 18 W 2× DDR3-800 2011-01-09
U5400 1.2 GHz 2010-05-25
Celeron P4600 2.0 GHz 667 MHz 35 W 2× DDR3-1066 2 MB 2010-09-26 $86
P4500 / P4505 1.86 GHz 2010-03-28 OEM
U3600 1.2 GHz 500 MHz 18 W 2× DDR3-800 2011-01-09 $134
U3400 / U3405 1.06 GHz 2× DDR3-800 / 1066 2010-05-25 OEM

Roadmap[edit]

The successor to Nehalem and Westmere is Sandy Bridge.

See also[edit]

References

Uncategorized

Arrandale

Arrandale

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This article is for the family of processors. For the community in British Columbia, Canada, see Arrandale, British Columbia
Arrandale
General Info
Launched 2010
Designed by Intel
Product code 80617
Performance
Max. CPU clock rate 1.06 GHz to 2.66 GHz
Cache
L2 cache 2×256 KB
L3 cache Up to 4 MB
Architecture and classification
Application Mobile
Min. feature size 32 nm
Microarchitecture Westmere
Instruction set x86x86-64MMXSSESSE2SSE3SSSE3SSE4.1SSE4.2AES-NI
Physical specifications
Cores
  • 2
Socket(s)
Products, models, variants
Brand name(s)
History
Successor Sandy Bridge

Arrandale is the code name for a family of mobile Intel processors, sold as mobile Intel Core i3, i5 and i7 as well as Celeron and Pentium.[1][2] It is closely related to the desktop Clarkdale processor; both use dual-core dies based on the Westmere 32 nm die shrink of the Nehalem microarchitecture, and have integrated Graphics as well as PCI Express and DMI links.

Arrandale is the successor of the 45 nm Core-microarchitecture-based Penryn processor that is used in many of the mobile Intel Core 2Celeron and Pentium Dual-Core processors. While Penryn typically used both a north bridge and a south bridge, Arrandale already contains the major northbridge components, which are the memory controller, PCI Express bus for external graphics, integrated graphics, and the DMI interface, making it possible to build more compact systems.

The Arrandale processor package contains two dies: the 32 nm processor die with the I/O connections, and the 45 nm Intel HD Graphics (Ironlake) controller and integrated memory controller die.[3] Physical separation of the processor die and memory controller die resulted in increased memory latency.

Arrandale was released on 7 January 2010, during CES 2010.[4]

Brand names[edit]

Arrandale processors were sold under the CeleronPentiumIntel Core i3Intel Core i5 and Intel Core i7 brand names, with only the Core i7 models using the full L3 cache and all features. Processors ending in E instead of M are embedded versions with support for PCIe bifurcation and ECC memory, while the regular mobile versions only support a single PCIe port and non-ECC memory. The Celeron versions of Arrandale have the smallest L3 cache of just 2 MB.[5]

Brand Name Model (list) L3 Cache size Thermal Design Power
Intel Celeron P4xxx 2 MB 35 W
U3xxx 18 W
Intel Pentium P6xxx 3 MB 35 W
U5xxx 18 W
Intel Core i3 i3-3xxM 3 MB 35 W
i3-3xxUM 18 W
Intel Core i5 i5-4xxM, i5-5xxM, i5-5xxE 3 MB 35 W
i5-4xxUM, i5-5xxUM 18 W
Intel Core i7 i7-6xxM, i7-6xxE 4 MB 35 W
i7-6xxLM, i7-6xxLE 25 W
i7-6xxUM, i7-6xxUE 18 W

See also[edit]

Uncategorized

Clarkdale (microprocessor)

Clarkdale (microprocessor)

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Clarkdale
General Info
Launched January 7, 2010
Designed by Intel
CPUID code 02065x
Product code 80616
Performance
Max. CPU clock rate 2.27 GHz to 3.6 GHz
Cache
L2 cache 2×256 KB
L3 cache 4 MB
Architecture and classification
Application Desktop
Min. feature size 32 nm
Microarchitecture Westmere
Instruction set x86x86-64MMXSSESSE2SSE3SSSE3SSE4.1SSE4.2AES-NI
Physical specifications
Cores
  • 2
Socket(s)
Products, models, variants
Brand name(s)

Clarkdale is the code name for an Intel processor, initially sold as desktop Intel Core i5 and Core i3 and Pentium.[1] It is closely related to the mobile Arrandale processor; both use dual-core dies based on the Westmere 32 nm die shrink of the Nehalem microarchitecture, and have integrated Graphics as well as PCI Express and DMI links.

Clarkdale is the successor of the 45 nm Core microarchitecture-based Wolfdale processor that is used in the many desktop Intel Core 2Celeron and Pentium Dual-Core processors. While Wolfdale typically used both a north bridge and a south bridge, Clarkdale already contains the major north bridge components, which are the memory controller, PCI Express for external graphics, integrated graphics and the DMI connector, making it possible to build more compact systems without a separate northbridge or discrete graphics as Lynnfield.

The Clarkdale processor package contains two dies: the 32 nm processor die with the I/O connections, and the 45 nm graphics and integrated memory controller die.[2] Physical separation of the processor die and memory controller die resulted in increased memory latency.

The CPUID for Clarkdale is family 6, model 37 (2065x). The mobile equivalent of Clarkdale is Arrandale.

Brand names[edit]

Clarkdale processors are sold under the Intel CorePentium and Celeron brand names, with varying feature sets. The Core i5 versions generally have all features enabled, with the Core i5-661 and Core i5-655K models lacking Intel VT-d and TXT like the Core i3, which also does not support Turbo Boost and AES new instructions. In addition, the Pentium and Celeron versions do not have SMT, and they can only use a reduced amount of third-level cache.

The Xeon L340x line has a lower clock frequency and thermal design power, and supports unbuffered ECC memory in addition to the features of the Core i5-6xx, but has support for the integrated graphics disabled.

Importantly, although the memory controller in Clarkdale processors is on-package, it is on a separate die from the CPU cores, and thus has increased latency compared to processor architectures which integrate it on-die with the main CPU cores.[3]

Brand Name Model (list) Logo L3 Cache size Thermal Design Power
Celeron G1xxx 2 MB 73 W
Pentium G6xxx 3 MB
Core i3 i3-5xx 4 MB
Core i5 i5-6xx 73–87 W
Xeon L340x 4 MB 30 W

See also[edit]